1. Field of the Invention
The present invention is generally in the field of signal processors and central processing units. In particular, the invention is in the field of very long instruction word (“VLIW”) processors.
2. Background Art
VLIW processors differ from the general conventional processors. One primary difference is that VLIW processors use very long instruction words which are, simply stated, a combination of instructions which are generally handled concurrently by the processor. A VLIW “packet” of instructions (also referred to as a “composite packet” in the present application) usually includes, in addition to the combination of instructions referred to above, other information which are needed for processing that particular combination of instructions. For example, each VLIW composite packet includes a template which specifies, among other things, the particular “instruction type” placed in each “instruction slot” of the composite packet. Examples of various instruction types are arithmetic instructions, logical instructions, branch instructions, or memory associated instructions. Each instruction type is usually assigned to one or two specific logic units for its execution (each such logic unit is appropriately called an “execution unit”).
A VLIW packet typically contains a number of instructions whose execution can begin in the same clock cycle. Instructions in a VLIW packet whose execution can begin in the same clock cycle form a single “issue group.” By definition, instructions belonging to a same issue group do not depend on the result of execution of other instructions in that same issue group. However, instructions in one issue group may depend on the result of execution of instructions in another issue group. The “length” of an issue group specifies how many instructions are in that issue group. For example, a particular issue group may have a length of two instructions. The template in a VLIW packet contains information as to which instructions in the VLIW packet belong to the same issue group. For example, in a certain VLIW processor there may be up to four issue groups in a VLIW packet. The template also contains information as to the length of each issue group.
Moreover, one or more instructions in a first VLIW packet may be “chained” to an issue group in a second VLIW packet. In other words, one or more instructions in the first VLIW packet may belong to an issue group in the second VLIW packet. Hence, the execution of the “chained” instruction (or instructions) will begin in the same clock cycle in which the execution of instructions in the issue group in the second VLIW packet begins. The template in the VLIW packet also contains information indicating which instruction (or instructions), if any, in the first VLIW packet is (or are) chained to an issue group in the second VLIW packet.
Information regarding the assigning of instructions to particular slots in a VLIW packet for execution in appropriate execution units, information as to the number and length of each issue group in the VLIW packet, and chaining information are among information which are contained in the template of the VLIW packet. The template in the VLIW processor may comprise a number of consecutive bits located next to each other or a number of bits that are spread throughout the VLIW packet.
A typical VLIW processor assembly language program contains assembly code for the instructions to be placed in a VLIW packet. Moreover, a typical VLIW processor assembly language program contains specific assembly code associated with execution of the instructions in the VLIW packet. Stated differently, a typical VLIW processor assembly language program contains not only the instructions to be executed by the processor, but assembly code containing information such as issue grouping and chaining of the instructions to be executed. From the assembly language code provided by the programmer, a VLIW packet must be encoded. Encoding involves determining an appropriate template for the VLIW packet and placing the template bits and the bits corresponding to each individual instruction in appropriate bit positions within the VLIW packet.
Present methods used for various generic processors cannot be easily and efficiently used to encode VLIW packets. One reason is that VLIW processors, unlike generic processors, have composite packets which include template bits in addition to the bits corresponding to the individual instructions. Accordingly, there is need in the art for a method and system tailored to encoding composite packets in VLIW processors.
Moreover, it is desirable to be able to simulate execution of the encoded composite VLIW packets before actually executing them on the VLIW processor itself. The VLIW packets are input to a process, called a simulator or simulation, which mimics execution of the VLIW packets on the VLIW processor. The simulation itself may be run on any suitable computer. As part of the simulation process, the encoded composite VLIW packets must be decoded from the bit patterns of the encoded composite VLIW packet back into assembly code for the instructions. In addition to decoding the bit patterns into assembly code for the instructions, the simulation also requires decoding the bit patterns into the assembly code associated with execution of the instructions. As such, there is need in the art to decode composite VLIW packets and also to simulate the VLIW processor's execution of the decoded composite packets.